The present invention relates to a receiving apparatus for and receiving method of receiving a digitally modulated digital signal, and more specifically to a receiving apparatus for and receiving method of receiving a digital signal in which real data and information indicating a transfer method therefor are multiplexed therein and decoding the real data step by step while decoding the transfer system.
The history of development in the field of integrated circuits enabling high speed processing of digital data and a coding technology in recent years indicates a trend of shifting of technology from an analog system to that based on a digital system. Especially, the trend is remarkable in the field of telecommunications, and services such as television broadcasting or satellite broadcasting are now shifting to those based on the digital system.
In a case of the digital broadcasting, the digitizing processing is executed to a signal indicating service information, and the resultant digital data is transferred. Among them, in the digital satellite broadcasting a carrier wave is modulated using digital data indicating contents of information to be transferred (digital modulation), the resultant signal is transmitted via a satellite and is directly received by a receiver installed in each house.
In a case where a signal subjected to digital modulation is transferred by means of cable communication, sometimes the signal can not accurately be received due to a quality of the transfer path, a transfer distance, or noise environment around the transfer path. On the contrary in a case where a modulated signal is transferred through a radio system like in the television broadcasting, because electric waves are used as carrier waves a quality of a transfer space as a transfer path becomes lower due to the influence of the climate or the like and sometimes the receiving conditions become worst.
To execute the modulation/demodulation with high reproducibility in transmitting and receiving signals and to overcome the problems as described above, in the radio communication, whether it be an analog or a digital communication system it is necessary to divide the radio frequency band to narrower frequency bands in order to realize a plurality of communication paths and to use each band area as one communication path.
Like in a case of the digital satellite broadcasting as described above, when a digitally modulated signal is transmitted through radio communications, as higher reproducibility is required for each bit constituting the digital data, generally to provide redundancy in transmission, the digital data to be digitally modulated is encoded with redundancy added to the real data. In the following description, digital data obtained by means of encoding the real data is defined as a data stream.
When redundancy of the digital data is increased its error correction capability is improved. Namely, even if a data stream with high redundancy includes many error bits in receiving, the error bits can be corrected, and the data stream can correctly be reproduced in transmission. At the same time, the data stream with high redundancy as described above has redundancy data added to the real data and the amount of data increases so that the transmission efficiency becomes disadvantageously lower.
For instance, when information such as an image or voice is transferred as a data stream including a few errors, the information is acceptable even if the data stream is disturbed a little in receiving, so that the information may be transferred by lowering the redundancy to a relatively low level to raise the transfer efficiency. On the other hand, in a data stream expressing a computer program or the like in which it is not admissible to have an error of even one bit, accurate reproduction of the information is required in receiving by raising the redundancy to a relatively high level.
As described above, even in a case of digital data with redundancy added to the real data, it is recognized simply as a bit array in receiving, and the redundancy included in the data stream can not be extracted. Therefore, information indicating what type of redundancy is included in which section of a multiplexed data (data configuration control signal) is further added to the data stream in transmission.
This data configuration control signal is generally called as TMCC (Transmission and Multiplexing Configuration Control), and the term TMCC signal is used also in the following description.
In a receiving apparatus for receiving a digital signal in which a data stream and a TMCC signal are multiplexed, the TMCC signal must accurately be received without fail to recognize redundancy of the data stream according to information indicating the TMCC signal and also to execute decoding processing for extracting and correcting real data from the data stream. Redundancy given to this TMCC signal is set to a relatively high level and also the redundancy is previously obtained in the receiving apparatus which insures recognition of the TMCC signal.
FIG. 1 is a block diagram showing general configuration of a transmitter based on the conventional technology. FIG. 1 especially shows an example of a transmitter for digital satellite transmission. In FIG. 1, the transmitter comprises an outer coding error control signal adding circuit 101 for encoding input signals TS1, TS2, . . . (described as input signal TS hereinafter), a frame forming circuit 102, an energy dispersal circuit 103, an interleaver 104, an inner coding error control signal adding circuit 105, a TMCC signal generating circuit 106 for encoding a TMCC signal, an outer coding error control signal adding circuit 107, an energy dispersal circuit 108, an inner coding error control signal adding circuit 109 and a modulating circuit 110.
It should be noted that, in FIG. 1, the input signal TS as an example of digital data is a digital data stream (transport stream) compressed by MPEG2 (Motion Picture Expert Group 2) which is one of the motion picture compressing systems. In this case, multiplexing means that, when 8 types of input signals TS1 to TS8 each indicating different information contents (such as programs provided by broadcasting stations), a data stream comprising an array of these input signals TS1 to TS8 is transferred using one carrier wave.
At first, a TMCC signal as transfer information for the input signal TS is generated in the TMCC signal generating circuit 106. The transfer information for the input signal TS indicates a position (timing) of each of the input signals TS multiplexed on a carrier wave and the transfer system (including the redundancy or the like).
The input signal TS is first inputted to the outer coding error control signal adding circuit 101. The outer coding error control signal adding circuit 101 is a circuit for adding a redundancy signal (an outer coding error control signal) enabling correction of an error byte by byte in a receiving apparatus to each input signal TS and outputting the added signal (described as input signal TSxe2x80x2 hereinafter). Namely, the outer coding error control signal adding circuit 101 is a circuit for adding redundancy to the input signal TS, and for instance the Reed Solomon encoding system is used for encoding the input signals TS.
The input signal TSxe2x80x2 outputted from the outer coding error control signal adding circuit 101 is inputted into the frame forming circuit 102. The frame forming circuit 102 is a circuit for forming a frame as a multiplexed data unit by multiplexing each input signal TSxe2x80x2 according to the transfer information indicated by a TMCC signal outputted from the TMCC signal generating circuit 106.
A signal outputted from the frame forming circuit in the units of frame is inputted into the energy dispersal circuit 103. The energy dispersal circuit 103 is a circuit for adding (scrambling) a pseudo random signal (an energy dispersal signal) to the digital data so that digital data constituting the input frame, namely the bit array will not be transferred as a long succession of bit xe2x80x9c0xe2x80x9d or bit xe2x80x9c1xe2x80x9d.
This circuit is required for detection of abnormality in a digital signal or to prevent a failure in the detection of a digital signal when a long succession of the same bits is required in the receiving side. As the pseudo random signal described above is required to be removed in the receiving side, also in the energy dispersal circuit 103 at which position of digital data the information indicating conditions for generation of a pseudo random signal such as random initial value is located is decided by referring to the transfer information indicated by a TMCC signal outputted from the TMCC signal generating circuit 106.
The signal scrambled in the energy dispersal circuit 103 is inputted into the interleaver 104. The interleaver 104 is a circuit for rearranging digital data indicated by the inputted signal in the units of byte to improve a burst error (successive errors continued for a long time) appearing within an extremely short period of time.
With this circuit, even when a burst error occurs in the rearranged digital signal, the processing for reproducing the rearranged digital signals (processing by the deinterleaver described later) is executed, so that errors appearing within an extremely short period of time can be distributed, which makes it possible to raise the error correction capability or recognition rate of transferred information. Also the information for rearrangement described above can be obtained from transfer information indicated by the TMCC signal outputted from the TMCC signal generating circuit 106.
The signals rearranged by the interleaver 104 are inputted into the Inner coding error control signal adding circuit 105. The inner cording error control signal adding circuit 105 is a circuit for adding a redundancy signal (inner coding error control signal) enabling correction of a random error which is an irregular error by a bit unit such as heat or noises generated in a transfer path of a receiving apparatus to an inputted signal. Namely, the inner coding error controls. Namely the inner coding error control signal adding circuit 105 is a circuit for adding redundancy to an inputted signal, and for instance, convolutional code is used.
FIG. 2 is a block diagram showing general configuration of an internal circuit for adding convolutional code in the inner coding error control signal adding circuit 105. The internal circuit shown in FIG. 2 comprises a shift transistor comprising six D latches 121 to 126, two EXOR circuits 127 and 128, and one puncture circuit 129, and executes coding for outputting 2-bit data in response to 1-bit input data. (quantity of information)/(quantity of information after coding) is called as coding ratio and the cording ratio in this internal circuit is 1/2.
In the internal circuit shown in FIG. 2, the initially inputted 6-bit serial data is stored in the order of input in the D latches 121 to 126 respectively. Namely, serial data successively inputted by 7 bits is converted to 7-bit parallel data according to the six input data retained in the D latches 121 to 126 and a 1-bit input data further inputted therein. Then the newly inputted input data and data stored in the D latch 122, D latch 123, D latch 125 and D latch 126 are inputted into the EXOR circuit 127, and the data is subjected to computing for exclusive OR in the circuit.
For instance, when input data of xe2x80x9c1xe2x80x9d is inputted in succession to the input signals inputted in the order of xe2x80x9c110110xe2x80x9d into the shift register described above, data indicating xe2x80x9c1xe2x80x9d is outputted from the EXOR circuit 127, while data of xe2x80x9c0xe2x80x9d is outputted from the EXOR circuit 128, and the output data is used as 2-bit data of xe2x80x9c10xe2x80x9d via the puncture circuit 129.
Herein 6-bit output data can be obtained from the 3-bit input data successively inputted into this internal circuit, but to improve the transfer efficiency, sometimes only 4 bits obtained by thinning the 6-bit output data by 2 bits is outputted as sending data. In this case, the coding ration can be expressed as 3/4, and compared to the coding ratio of 1/2 the redundancy becomes lower with the transfer efficiency improved, but at the same time the error correction capability becomes lower. Therefore, it becomes possible to control redundancy by changing a degree of thinning of data, and this processing for thinning of data is called puncturing, and the puncturing circuit 129 is a circuit for executing this puncturing.
As also the TMC signal outputted from the TMCC signal generating circuit 106 must be multiplexed with a data stream such as an input signal TS for transfer, the processing for enabling the error correction as described above is executed. In FIG. 1, the TMCC signal outputted from the TMCC signal generating circuit 106 is inputted into the outer coding error control signal adding circuit 101, frame forming circuit 102, energy dispersal circuit 103, interleaver 104 and inner cording error control signal adding circuit 105, and is also inputted into the outer coding error control signal adding circuit 107.
The outer cording error control signal adding circuit 107 is a circuit for, like the outer cording error control signal adding circuit 101, outputting a signal with a redundancy signal for correcting an error in the units of byte added thereto in response to the inputted TMCC signal. A signal outputted from the outer cording control signal adding circuit 107 is inputted into the energy dispersal circuit 108, and is subjected to scrambling like in the energy dispersal circuit 103.
The signal scrambled in the energy dispersal circuit 108 is inputted into the inner coding error control signal adding circuit 109. The inner coding error control signal adding circuit 109 is a circuit for, like the inner cording error control signal adding circuit 105, adding a signal with a redundancy signal for correction of an error in the units of bit added thereto in response to an input signal.
A signal outputted from the inner cording error control signal adding circuit 105, namely a multiplexed data stream with redundancy added thereto, and a signal outputted from the inner coding error control signal adding circuit 109, namely a TMCC signal with redundancy added thereto are inputted into the modulating circuit 110 and a signal with a TNCC signal multiplexed to the frame formed as a new frame and is also subjected to digital modulation.
Digital modulation executed in the modulating circuit 110 could be amplitude modulation (ASK), frequency modulation (FSK), or phase modulation (PSK), but herein description is made with reference to digital phase modulation.
The digital phase modulation is a system in which digital data comprising bits of xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d correlated to a phase and information is transferred by switching this phase for the carrier waves. The digital phase modulating system is further classified into three systems of BPSK, QPSK (or 4PSK) and 8PSK according to a system of correlating a phase.
FIG. 3 is an explanatory view showing the digital phase modulating system. BPSK is a system in which, as shown in FIG. 3, for 1-bit digital data, for instance xe2x80x9c0xe2x80x9d is correlated to a phase difference of 0 degree and xe2x80x9c1xe2x80x9d is correlated to a phase difference of 180 degrees. QPSK is a system, for 2-bit digital data, for instance, xe2x80x9c00xe2x80x9d, xe2x80x9c01xe2x80x9d, xe2x80x9c11xe2x80x9d, and xe2x80x9c10xe2x80x9d are correlated to a phase difference of 45 degrees, a phase difference of 135 degrees, a phase difference of 225 degrees and a phase difference of 315 degrees respectively.
Further, 8PSK is a system in which, for 3-bit digital data, for instance xe2x80x9c000xe2x80x9d, xe2x80x9c001xe2x80x9d, xe2x80x9c011xe2x80x9d, xe2x80x9c010xe2x80x9d, xe2x80x9c100xe2x80x9d, xe2x80x9c101xe2x80x9d, xe2x80x9c111xe2x80x9d, xe2x80x9c110xe2x80x9d are correlated to a phase difference of 0 degree, a phase difference of 45 degree, a phase difference of 90 degree, a phase difference of 135 degree, a phase difference of 180 degree, a phase difference of 225 degree, a phase difference of 270 degree and a phase difference of 315 degree respectively.
Namely, by checking a phase state (transfer symbol) of a carrier wave, it is possible to transfer 1-bit information in BPSK, 2-bit information in QPSK, and 3-bit information in 8PSK. However, as the transfer efficiency becomes higher, adjacent transfer symbols come closer to each other, so that discrimination of one phase from another becomes difficult, which makes it easier for information error to occur, and because of this disadvantageous characteristics, any of the three phase modulating systems is selected according to the characteristics of information to be transferred.
As described above, in the digital phase modulation, sometimes various types of data based on these different systems are multiplexed, and the modulating circuit 110 executes phase modulation based on any of the three systems described above to each discrete data stream.
FIG. 4 is an explanatory view showing one example of configuration of a digital signal transferred from the transmitter described above. Especially, FIG. 4 shows an example of a digital signal in the digital satellite broadcasting. In this example, as a data stream, QPSK modulated stream with the coding ratio of 3/4, QPSK modulated stream with the coding ratio of 1/2, and BPSK modulated stream with the coding ratio of 1/2 are multiplexed. In the input signal TS described above, TS1, TS2 and TS3 correspond to the data streams respectively.
In FIG. 4, each row is called frame, and 8 frames are treated as one block of information. This block consisting of the 8 frames is called super frame, and the frames and super frames are formed in the frame forming circuit 102 described above. In addition, a synchronous word one is located at a head of each frame, and in succession to this synchronous word, TMCC signals (TMCC1 to TMCC6) are located up to the first 6 frames, and parity signals (parity 1 and parity 2) are located in the remaining two frames.
In succession to the TMCC signal (TMCC1) in the header frame, a synchronous word two is located, and the multiplexed data streams follow the synchronous word. In the frame other than the header frame a synchronous word three is located in succession to the TMCC signal or the parity signal and the multiplexed data streams follow this.
The synchronous word one is a signal defining a header of each frame, and a specific bit pattern indicating a header of a frame is given thereto. The TMCC signal located in succession to the frame head includes information for a transfer system for each of the multiplexed data streams (including redundancy information) and multiplexed information concerning positions (configuration arrangement). Further, the parity signal indicates redundancy added to a super frame, and is a redundancy signal based on Reed Solomon code added thereto in the outer coding error control signal adding circuit 101.
The synchronous word two indicates a header frame in a super frame, it is a signal defining a border between a TMCC signal and a data stream, and especially a specific bit pattern discriminated from a synchronous word three is given thereto.
Actually, a series of TMCC signals TMCC1 to TMCC 6 generated for one super frame are generated by the TMCC signal generating circuit 106 shown in FIG. 1. And the TMCC signal is outputted by the outer coding error control adding circuit 107 shown in FIG. 1 as a data array of TMCC1 to TMCC6+parities 1 and 2.
On the other hand, each of the input signals TS (TS1, TS2 and TS3) is outputted by the outer coding error control signal adding circuit 101 shown in FIG. 1 as TS+parity, and this data corresponds to the QPSK (3/4), QPSK (1/2) and BPSK (1/2) shown in FIG. 4 respectively. Namely, an outer coding parity is included in the QPSK (3/4), QPSK (1/2) and BPSK (1/2).
FIG. 5 is a block diagram showing general configuration of a receiving apparatus based on the conventional technology. FIG. 5 shows an example of a receiving apparatus for digital satellite broadcasting corresponding to the transmitting apparatus shown in FIG. 1. In FIG. 5, the receiving apparatus comprises a phase demodulating apparatus 130 comprising a phase demodulating circuit, and a transmitting code decoding apparatus 140.
The transmitting code decoding apparatus 140 comprises a Viterbi decoding circuit 131, a synchronism detecting circuit 132, an energy dispersal signal removing circuit 133 for decoding the TMCC signal, an outer coding error correcting circuit 134, a TMCC register 135, a deinterleaver 136 for decoding a data stream, an energy dispersal signal removing circuit 137, an outer coding error correcting circuit 138 and a TS selecting circuit 139.
A digital signal transmitted from a transmitting apparatus is received by the receiving apparatus, and at first is subjected to demodulation by the phase demodulating apparatus 130. The phase demodulating apparatus 130 is a circuit for extracting digital data from the received digital signal in a state before execution of modulation in the modulating circuit 110 in the transmitting apparatus, and in this example, digital phase demodulation is executed to a carrier wave subjected to digital phase modulation.
The signal demodulated by the phase demodulating apparatus 130 is inputted to the Viterbi decoding circuit 131 in the transmitting code decoding apparatus 140. The Viterbi decoding circuit 131 is a circuit for decoding a signal encoded by addition of a redundancy signal in the inner coding error control signal adding circuit 105 and inner coding error control signal adding circuit 109 in the transmitter, and especially decodes convolutional code.
The processing for decoding by the Viterbi decoding circuit 131 is a processing common to both the TMCC signal and the data stream included in a received digital signal, and the subsequent processing flow for a TMCC signal is different from that for a data stream, so that the processing for recognizing a TMCC signal and a data stream from a digital signal and extracting the recognized TMCC signal or data stream is required. Especially in a case of a data stream, a plurality of data streams are multiplied and the multiplexed data stream is transferred, so that, to extract each discrete data stream from the multiplexed data stream, information included in the TMCC signal is required.
The synchronism detecting circuit 132 is a circuit for receiving a signal decoded by the Viterbi decoding circuit 131 and for recognizing the TMCC signal and data stream described above. The TMCC signal and data stream recognized and extracted in the synchronism detecting circuit 132 is subjected to processing specific to each of the TMCC signal and data stream, but for the reasons described above, it is necessary to completely decode the TMCC signal before the data stream is completely decoded. Extraction of the TMCC signal by the synchronism detecting circuit 132 is executed by detecting the synchronous word one, synchronous word two, or synchronous word three in the super frame shown in FIG. 4.
The TMCC signal outputted from the synchronism detecting circuit 132 is inputted into the energy dispersal signal removing circuit 133. The energy dispersal signal removing circuit 133 is a circuit for removing a pseudo random signal added to the TMCC signal in the energy dispersal circuit 108 in the transmitting apparatus.
The TMCC signal from which a pseudo random signal is removed in the energy dispersal signal removing circuit 133 is then inputted into the outer coding error correcting circuit 134. The outer coding error correcting circuit 134 is a circuit for correcting an error in he TMCC signal encoded by the outer coding error control signal adding circuit 107 in the transmitting apparatus according to redundancy added thereto and obtaining only the original TMCC signal indicating transfer information for the data stream. It should be noted that, a Reed Solomon decoding circuit is used as the outer coding error correcting circuit 134 when Reed Solomon code is used in the transmitting apparatus.
The TMCC signal obtained by the outer coding error correcting circuit 134 is stored in a TMCC register 135, and the TMCC signal stored in this TMCC register 135 is used for decoding a data stream extracted in the synchronism detecting circuit 132. It should be noted that, the transfer information such as a redundancy degree or a pseudo random initial value required for decoding of a TMCC signal is previously obtained by the receiving apparatus.
The data stream extracted in the synchronism detecting circuit 132 is inputted into the deinterleaver 136. The deinterleaver 136 returns a sequence of the data stream to the original one by canceling rearrangement executed by the interleaver 104 in the transmitting apparatus.
The data stream restored by the deinterleaver 136 is then inputted into the energy dispersal signal removing circuit 137. The energy dispersal signal removing circuit 137 is a circuit for, like the energy dispersal signal removing circuit 133, removing a pseudo random signal added to a data stream in the energy dispersal circuit 103 in the transmitting apparatus.
The data stream from which the pseudo random signal is removed in the energy dispersal signal removing circuit 137 is then inputted into the outer coding error correcting circuit 138. The outer coding error correcting circuit 138 is a circuit for correcting an error in a data stream encoded in the outer cording error control signal adding circuit 101 in the transmitting apparatus, like the outer coding error correcting circuit 134, according to the TMCC signal stored in the TMCC register 135.
The data stream having been subjected to error correction in the outer coding error correcting circuit 138 is inputted into the TS selecting circuit 139. The TS selecting circuit 139 is a circuit for extracting each discrete data stream from a multiplexed data stream according to the TMCC signal stored in the TMCC register 135 and selecting a desired data stream, namely any of the input signals TS inputted by the transmitting apparatus.
The TS signal selected and outputted from the TS selecting circuit 139 is inputted into an MPEG decoding circuit (not shown) in the downstream therefrom to enable display of a motion picture on a display unit.
In the processing for receiving signals described above, existence of a TMCC signal is always necessary for decoding a multiplexed data stream, but irrespective of the fact that a TMCC signal included in a received digital signal is not different from the TMCC signal already stored in the TMCC register 135, namely that the TMCC signal has not been updated, the TMCC signal is rewritten in the TMCC register each time, which disadvantageously caused increase in power consumption.
To eliminate the unnecessary data write processing as described above, a method is conceivable in which all of bits in a newly received TMCC signal are compared to all bits in the TMCC signal already stored in the TMCC register 135 to check an updating state of the TMCC signal. FIG. 6 is a block diagram showing general configuration of a conventional type of TMCC obtaining circuit for comparing all of TMCC signals to each other. This TMCC obtaining circuit is a circuit for replacing the TMCC register 135 in the receiving apparatus described above.
In FIG. 6, assuming, for instance, that a TMCC signal indicating transfer information for a data stream comprises 379 bits, a 379-bit TMCC signal newly received and inputted into the TMCC obtaining circuit is once inputted into a buffer 141. Then a TMCC signal outputted from this buffer 141 and the TMCC signal already stored in the register 142 are inputted into a comparing circuit 143.
The comparing circuit compares all of 379 bits in each of the two types of TMCC signals inputted therein bit by bit to each other, and when the two TMCC signals are inconsistent outputs a signal as a write instruction. When the register 142 receives a signal indicating a write instruction from the comparing circuit 143, the TMCC signal stored in the buffer 141 is written in the register 142. With this operation, the processing for updating of the TMCC signal is complete and the data stream is decoded according to this TMCC signal.
However, to compare all bits in each of TMCC signals composed of, for instance, 379 bits bit by bit to each other a large scale comparing circuit 143 is required, which makes it impossible to downsize the entire receiving apparatus, and further a large power is required to operate the large scale comparing circuit 143 as described above, which in turn disadvantageously increases the power consumption.
To solve the problems as described above, a method is conceivable in which updating instruction information for a TMCC signal is added to each TMCC signal and only the updating instruction information added to each TMCC signal is compared to each other to reduce a work load on the comparing circuit 143. FIG. 7 is a block diagram showing general configuration of the TMCC obtaining circuit based on the conventional technology for comparing the updating instruction information to each other. Herein it is assumed that the updating instruction information is numerical information comprising 5 bits and the updating instruction information is added to the header of each of 379-bit TMCC signal with the multiplexed TMCC signal transferred from a transmitting apparatus.
In FIG. 7, in the TMCC signal comprising 379+5 bits obtained by adding the 5-bit updating instruction information to a 379-bit TMCC signal, the header 5-bit corresponding to the updating instruction information is retained in an updating instruction information retaining area 153, while 379 bits corresponding to the original TMCC signal is retained in the buffer 151. The updating instruction information outputted from this updating instruction information retaining area 153 and updating instruction information already stored in the updating instruction information storing area 154 are inputted into the comparing circuit 155.
The comparing circuit 155 compares the two types of updating instruction information inputted therein to each other, and when the two types of updating instruction information are inconsistent outputs a signal as a write instruction. Especially, by previously deciding, for instance, that, when the TMCC signal is updated in the sending side, a numeral value of the 5-bit updating instruction information is increased by 1, and this can be used to determine whether the TMCC signal has been updated or not. The register 152 receives a signal indicating a write instruction from the comparing circuit 155, and then writes the TMCC signal retained in the buffer 151 in the register 152. With this operation, the processing for updating the TMCC signal is complete and the data stream is decoded according to this updated TMCC signal.
With this configuration, it is possible to determined whether updating of a TNCC signal is required or not by comparing only 5 bits in each of the TMCC signals to each other in the comparing circuit 155, and the scale of a circuit as the comparing circuit 155 does not cause a problem.
However, when turning ON a power for a receiving apparatus for activating it, generally all bits of the register for storing the updating instruction information are set to a fixed value such as xe2x80x9c0xe2x80x9d. In this step, if the updating instruction information newly received accidentally coincides to this fixed value of xe2x80x9c0xe2x80x9d the comparing circuit 155 determines that the newly received updating instruction information is coincident to that already stored in the register, and a signal as a write instruction to the register is not outputted, which creates problems in practical operation.
In a case of a numerical value indicating the updating instruction information, whether each TMCC signal has been updated or not can be determined continuously for the same carrier wave, but if a receiving carrier wave is switched to another one, even if actually an updated TMCC signal is transmitted and when updating instruction information newly received accidentally coincides to the updating instruction information stored when the carrier wave before switching to a new one was received the write instruction signal is not outputted from the comparing circuit 155. Namely, in the case as described above, there occurs the problem that, although a TMCC signal has been updated a data stream is not decoded according to the new TMCC signal.
To solve the problem described above, a method is conceivable in which, when an image signal is not detected for a long period of time in the MPEG decoding circuit or the like in the downstream therefrom, an abnormal state detection signal is inputted to compulsorily rewrite the TMCC signal stored in a register. FIG. 8 is a block diagram showing general configuration of a TMCC obtaining circuit based on the conventional technology in which an abnormal state detection signal is issued in the case as described above.
In FIG. 8, there is provided an OR circuit 160 which outputs a write signal to the register 152 when an inconsistency signal is outputted from the comparing circuit 155, or when an abnormal state detection signal is outputted from the MPEG decoding circuit or the like.
However, in the method based on the conventional technology, a certain period of time is required for detecting an error in an image signal in the MPEG decoding circuit or the like, so that a long period of time is required for determination as to whether each TMCC signal has been updated or not and until a normal image is displayed, and during this a normal image is not outputted, which sometimes causes misunderstanding that, for instance, a broadcasting accident has occurred. As described above, in any of the TMCC signal obtaining circuit (method) based on the conventional technology as described above, it is not possible to quickly and efficiently obtain a TMCC signal.
It is an object of the present invention to make it possible to quickly and efficiently obtain a TMCC signal as a data configuration control signal with simple and small-scale configuration.
With the present invention, when a decoding complete signal outputted from a decoding complete signal outputting unit first after a synchronism detection signal indicating detection of synchronism of a digital signal outputted from the synchronism detecting unit is received, a TMCC signal is updated by a data configuration control signal updating unit, so that, for instance when power supply to a receiving apparatus is started and the receiving apparatus is activated or when synchronism is established again, for instance, after a carrier wave is changed, updating of the TMCC signal can be executed simultaneously when decoding of the TMCC signal is complete first, and because of this configuration, it becomes possible to quickly obtain the latest TMCC signal with small-scale circuit configuration.
According to one feature of the present invention, there are provided a pulse outputting unit and a synchronous state maintaining unit and in the state where a synchronism detection signal has been inputted and the synchronous state is maintained and further a decoding complete signal is inputted then the TMCC signal used for decoding a data stream is updated to the newly received TMCC signal. Therefore, when power supply to a receiving apparatus is started and the receiving apparatus is activated or when synchronism is established again after a carrier wave is changed to another one, updating of the TMCC signal can be executed when decoding of a TMCC signal is complete first, hence, it becomes possible to quickly obtain the latest TMCC signal with small-scale circuit configuration.
According to one feature of the present invention, there is provided a data configuration control signal updating unit for changing a TMCC signal used for decoding a data stream to a newly received TMCC signal in the state when a synchronism detection signal shows a synchronous state, when a comparison signal outputted according to a result of comparison between updating instruction information already stored and updating instruction information newly received and decoded indicates inconsistency, and at the same time when a decoding complete signal indicates completion of decoding of the TMCC signal. Therefore, after a TMCC signal is updated once after detection of synchronism of a digital signal, only when the newly received updating instruction information is different from the updating instruction information already stored the updating of the TMCC signal is executed, Hence, it becomes possible to efficiently and quickly obtain the latest TMCC signal.
According to one feature of the present invention, as a synchronism detection signal inputted into the data configuration control signal updating unit a recognized state signal indicating the state where recognition of a data stream and a TMCC signal is complete is used, so that a circuit already existing in the receiving apparatus can be used without adding a circuit for outputting a synchronism detection signal. Therefore, it becomes possible to prevent the apparatus configuration from becoming more complicated and also to always obtain the latest TMCC signal with a small-scale configuration.
According to one feature of the present invention, as the synchronism detection signal inputted into the data configuration control signal updating unit a signal indicating completion of demodulation of a digital signal outputted from a digital demodulating circuit is used, so that a circuit already existing in the receiving apparatus can be used without adding a circuit for outputting a synchronism detection signal. Therefore, it becomes possible to prevent the apparatus configuration from becoming more complicated and also to always obtain the latest TMCC signal with a small-scale configuration.
According to one feature of the present invention, as the synchronism detection signal inputted into the data configuration control signal updating unit a signal indicating a phase-demodulated state of a digital signal outputted from a digital phase-demodulating circuit is used, so that a circuit already existing in the receiving apparatus can be used without adding a circuit for outputting a synchronism detection signal. Therefore, it becomes possible to prevent the apparatus configuration from becoming more complicated and also to always obtain the latest TMCC signal with a small-scale configuration.
According to one feature of the present invention, there is provided a selecting unit for selecting either a recognized state signal outputted from the synchronism detecting unit or a demodulate state signal outputted from a digitally demodulating unit and outputting the selected signal as a synchronism detection signal into the data configuration control signal updating unit so that various types of signals each indicating a synchronous state previously prepared in a receiving apparatus can be used according to the current situation. Therefore, it can be determined more flexibly as to whether updating of a TMCC signal has been executed or not.
According to one feature of the present invention, there is provided a selecting unit for selecting either a recognized state signal outputted from the synchronism detecting unit or a demodulated state signal outputted from a digitally phase-modulating unit and outputting the selected signal as the synchronism detection signal into the data configuration control signal updating unit, so that various types of signals each indicating a synchronous state previously prepared in a receiving apparatus can be used according to the current situation. Therefore, it can be determined more flexibly as to whether updating of a TMCC signal has been executed or not.
According to one feature of the present invention, a TMCC signal is updated when decoding of a TMCC signal is completed first after synchronism of a digital signal is detected. Thus, updating of a TMCC signal is executed when decoding of a TMCC signal is completed first after power supply to a receiving apparatus is started and the receiving apparatus is activated or when a carrier wave is switched to another one. Therefore, it is possible to quickly and efficiently obtain the latest TMCC signal.
According to one feature of the present invention, when decoding of a TMCC signal included in a received digital signal is complete after synchronism of the received digital signal is detected and in the state where updating instruction information already stored is not coincident to newly received updating instruction information, a TMCC signal used for decoding a data stream is changed to the newly received TMCC signal. Thus, after a TMCC signal is updated first after synchronism of a digital signal is detected, only when the newly received updating instruction information is different from the updating instruction information already stored, updating of a TMCC signal can be executed, therefore, it is possible to efficiently and quickly obtain a TMCC signal.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.